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HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
.eatures
x
IDT71V321S/L IDT71V421S/L
x
x
High-speed access - Commercial: 25/35/55ns (max.) - Industrial: 25ns (max.) Low-power operation - IDT71V321/IDT71V421S -- Active: 325mW (typ.) -- Standby: 5mW (typ.) - IDT71V321/V421L -- Active: 325mW (typ.) -- Standby: 1mW (typ.) Two INT flags for port-to-port communications
x
x x x x x x
x
MASTER IDT71V321 easily expands data bus width to 16or-more-bits using SLAVE IDT71V421 On-chip port arbitration logic (IDT71V321 only) BUSY output flag on IDT71V321; BUSY input on IDT71V421 Fully asynchronous operation from either port Battery backup operation--2V data retention (L only) TTL-compatible, single 3.3V power supply Available in 52-pin PLCC, 64-pin TQFP and STQFP packages Industrial temperature range (-40C to +85C) is available for selected speeds
.unctional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL
(1,2)
I/O0R-I/O7R I/O Control BUSYR A10R A0R
(1,2)
A10L A0L
Address Decoder
11
MEMORY ARRAY
11
Address Decoder
CEL OEL R/WL
ARBITRATION and INTERRUPT LOGIC
CER OER R/WR
INTL
(2)
INTR
3026 drw 01
(2)
NOTES: 1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input. 2. BUSY and INT are totem-pole outputs.
AUGUST 2001
1
(c)2001 Integrated Device Technology, Inc. DSC-3026/8
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (L) versions offer battery backup data retention capability, with each DualPort typically consuming 200W from a 2V battery. The IDT71V321/IDT71V421 devices are packaged in a 52-pin PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad flatpack).
Pin Configurations(1,2,3)
INDEX A1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
87 6 5 4 3 2 1 52 51 50 49 48 47 46 45 9 44 10 43 11 42 12 IDT71V321/421J 41 13 J52-1(4) 40 14 52-Pin PLCC 39 15 Top View(5) 38 16 37 17 36 18 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33
V CC CER
R/WR BUSYR INTR A10R
OER A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O7R
, 3026 drw 02
I/O 4L I/O 5L I/O 6L I/O 7L NC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
INTL BUSYL R/WL CEL
A 0L OEL A 10L
INDEX
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C A10L INTL BUSYL R/W L CEL VCC VCC CER R/WR BUSYR INTR A10R N/C N/C
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
OEL A0L A1L A 2L A3L A4L A 5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT71V321/421PF or TF PP64-1(4) & PN64-1(4) 64-Pin STQFP 64-Pin TQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A 0R A 1R A 2R A 3R A 4R A 5R A 6R N/C A 7R A 8R A 9R N/C N/C I/O7R I/O 6R
I/O3L N/C I/O 4L I/O 5L I/O 6L I/O 7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3026 drw 03
2 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V
3026 tbl 02
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -65 to +150 50
C
o
C C
o
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
mA
3026 tbl 01
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3
(1)
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
Typ. 3.3 0
____ ____
Max. 3.6 0 VCC+0.3 0.8
(2)
Unit V V V V
3026 tbl 03
Capacitance(1)
Symbol CIN COUT
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 20ns. 2. VTERM must not exceed Vcc + 0.3V.
(TA = +25C, f = 1.0MHz) TQ.P Only
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
3026 tbl 04
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V 0.3V)
71V321S 71V421S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current
(1)
71V321L 71V421L Min.
___
Test Conditions VCC = 3.6V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC VCC = 3.6V IOL = 4mA IOH = -4mA
Min.
___
Max. 10 10 0.4
___
Max. 5 5 0.4
___
Unit A A V V
3026 tbl 05
Output Leakage Current Output Low Voltage Output High Voltage
___
___
___
___
2.4
2.4
NOTE: 1. At VCC < 2.0V input leakages are undefined.
3 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) (VCC = 3.3V 0.3V)
71V321X25 71V421X25 Com'l & Ind Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. 55 55 55 55 15 15 15 15 25 25 25 25 1.0 0.2 1.0 0.2 25 25 25 25 Max. 130 100 150 130 35 20 50 35 75 55 95 75 5 3 10 6 70 55 85 70 71V321X35 71V421X35 Com'l Only Typ. 55 55
___
71V321X55 71V421X55 Com'l Only Typ. 55 55
___
Max. 125 95
___
Max. 115 85
___
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CER = CEL = VIH SEMR = SEML = VIH f = fMAX(3)
15 15
___
35 20
___
15 15
___
35 20
___
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
CE"A" = VIL and CE"B" = VIH (5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3)
25 25
___
70 50
___
25 25
___
60 40
___
mA
ISB3
Full Standby Current (Both Po rts - All CMOS Level Inputs)
1.0 0.2
___
5 3
___
1.0 0.2
___
5 3
___
mA
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
25 25
___
65 50
___
25 25
___
55 40
___
mA
3026 tbl 06
NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = 3.3V, TA = +25C, and are not production tested. ICCDC = 70mA (Typ.). 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Data Retention Characteristics (L Version Only)
Symbol VDR ICCDR tCDR (3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V COM'L. IND. Test Condition Min. 2.0
___
Typ.
___
(1)
Max. 0 1500 4000
___
Unit V A A V V
3026 tbl 07
100 100
___
___
0 tR
(3)
tRC
(2)
___
___
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but not production tested.
4 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2
3026 tbl 08
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
3.0V tCDR
3.0V tR
CE VIH
VDR VIH
3026 drw 04 ,
3.3V 590 DATAOUT BUSY INT 435 DATAOUT 30pF 435
3.3V 590
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * Including scope and jig.
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(2)
71V321X25 71V421X25 Com 'l & Ind Sym bol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2)
71V321X35 71V421X35 Com 'l Only Min. Max.
71V321X55 71V421X55 Com 'l Only Min. Max. Unit
Param eter
Min.
Max.
25
____ ____ ____
____
35
____ ____ ____
____
55
____ ____ ____
____
ns ns ns ns ns ns ns ns ns
3026 tbl 09
25 25 12
____ ____
35 35 20
____ ____
55 55 25
____ ____
3 0
____
3 0
____
3 0
____
Output High-Z Time (1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2)
12
____
15
____
30
____
0
____
0
____
0
____
50
50
50
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L).
5 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC ADDRESS tAA tOH DATAOUT BUSYOUT tBDD (2,3)
3026 drw 06
tOH DATA VALID
PREVIOUS DATA VALID
NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
tACE CE tAOE OE tLZ (1) DATAOUT tLZ ICC CURRENT ISS tPU 50%
(1) (4)
tHZ (2)
tHZ VALID DATA tPD
(4)
(2)
50%
3026 drw 07
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4)
71V321X25 71V421X25 Com'l & Ind Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (5) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (3) Write Enable to Output in High-Z Output Active from End-of-Write
(1,2) (1,2)
71V321X35 71V421X35 Com'l Only Min. Max.
71V321X55 71V421X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
25 20 20 0 20 0 12
____
____
35 30 30 0 30 0 20
____
____
55 40 40 0 40 0 20
____
____
ns ns ns ns ns ns ns ns ns ns ns
3026 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
12
____
15
____
30
____
0
____
0
____
0
____
15
____
15
____
30
____
(1,2)
0
0
0
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. 'X' in part numbers indicates power rating (S or L). 5. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
7 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC ADDRESS tHZ (7) OE tAW CE tAS(6) R/W tWZ (7) DATAOUT
(4)
tWP(2)
tWR (3) tOW
tHZ (7)
(4)
tDW DATAIN
tDH
3026 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC ADDRESS tAW CE tAS (6) R/W tDW DATA IN
3026 drw 09
tEW (2)
tWR
(3)
tDH
NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
8 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6)
71V321X25 71V421X25 Com'l & Ind Symbol BUSY Timing (For Master IDT71V321 Only) tBAA tBDA tBAC tBDC tWH tWDD tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY(5) Write Pulse to Data Delay
(1) (1)
____ ____ ____ ____
71V321X35 71V421X35 Com'l Only Min. Max.
71V321X55 71V421X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20
____
____ ____ ____ ____
20 20 20 20
____
____ ____ ____ ____
30 30 30 30
____
ns ns ns ns ns ns ns ns ns
12
____ ____
15
____ ____
20
____ ____
50 35
____
60 45
____
80 65
____
Write Data Valid to Read Data Delay Arbitration Priority Set-up Time BUSY Disable to Valid Data
(3) (2)
5
____
5
____
5
____
30
30
45
BUSY Timing (For Slave IDT71V421 Only) tWB tWH tWDD tDDD BUSY Input to Write (4) Write Hold After BUSY
(5) (1)
0 12
____ ____
____ ____
0 15
____ ____
____ ____
0 20
____ ____
____ ____
ns ns ns ns
3026 tbl 11
Write Pulse to Data Delay
50 35
60 45
80 65
Write Data Valid to Read Data Delay (1)
NOTES: 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 4. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT"B" VALID tDDD
(1)
tDH
VALID
MATCH tBDA tBDD
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
3026 drw 10
9 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(4)
tWP R/W"A" tWB(3) BUSY"B" tWH R/W"B"
(2) (1) ,
NOTES: 1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. tWB is for the slave version (71V421). 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
3026 drw 11
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A" AND "B" CE"B" tAPS(2) CE"A" tBAC BUSY"A"
3026 drw 12
ADDRESSES MATCH
tBDC
Timing Waveform of BUSY Arbritration Controlled by Address Match Timing(1)
tRC ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
3026 drw 13 (2)
OR
tWC ADDRESSES DO NOT MATCH
ADDRESSES MATCH
tBDA
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).
10 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1)
71V 321X25 71V 421X25 Com 'l & Ind Sym bol INTERRUPT TIM ING tAS tWR tINS tINR A d d re s s S et-up Tim e W rite Rec o v e ry Tim e Inte rrup t S e t Tim e Inte rrup t Re se t Tim e 0 0
____ ____ ____ ____
71V 321X35 71V 421X35 Com 'l Only M in. M ax.
71V 321X55 71V 421X55 Com 'l Only M in. M ax. Unit
Param eter
M in.
M ax.
0 0
____ ____
____ ____
0 0
____ ____
____ ____
ns ns ns ns
3026 tbl 12
25 25
25 25
45 45
NOTES: 1. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Interrupt Mode(1)
SET INT
tWC ADDR"A" INTERRUPT ADDRESS tAS (3) R/W"A" tINS (3) INT"B"
3026 drw 14 (2)
tWR(4)
CLEAR INT
tRC ADDR"B" tAS(3) OE"B" tINR(3) INT"A"
3026 drw 15
INTERRUPT CLEAR ADDRESS(2)
NOTES:. 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1) R/W X X L H H CE H H L L L OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Deselected and in PowerDown Mode. ISB2 or ISB4 CER = CEL = VIH, Power-Down Mode ISB1 or ISB3 Data on Port Written Into Memory (2) Data in Memory Output on Port(3) High-impedance Outputs
3026 tbl 13
NOTES: 1. A0L - A10L A0R - A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = High-impedance.
Table II. Interrupt .lag(1,4)
Left Port R/WL L X X X CEL L X X L OEL X X X L A10L-A0L 7FF X X 7FE INTL X X L(3) H
(2)
Right Port R/WR X X L X CER X L L X OER X L X X A10R-A0R X 7FF 7FE X INTR L(2) H
(3)
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
3026 tbl 14
X X
NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON'T CARE
Table III Address BUSY Arbitration
Inputs CEL X H X L CER X X H L AOL-A10L AOR-A10R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
3026 tbl 15
NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT71V321 (master). Both are inputs for IDT71V421 (slave). BUSYX outputs on the IDT71V321 are totem-pole. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
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IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
.unctional Description
The IDT7V1321/IDT71V421 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71V321/IDT71V421 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted.
being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic Master/Slave Arrays
Interrupts
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table II. The left port clears the interrupt by accessing address location 7FE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation.
When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71V321/IDT71V421 SRAMs the BUSY pin is an output if the part is Master (IDT71V321), and the BUSY pin is an input if the part is a Slave (IDT71V421) as shown in Figure 3.
DECODER
BUSYR
3026 drw 16
MASTER Dual Port RAM BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR
MASTER Dual Port RAM BUSYL BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. The BUSY outputs on the IDT71V321 RAM master are totem-pole type outputs and do not require pull-up resistors to operate. If these RAMs are
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
13 6.42
IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range Blank I(1)
Commercial (0C to +70C) Industrial (-40C to +85C)
J PF TF 25 35 55
52-pin PLCC (J52-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1) Commercial & Industrial Commercial Only Commercial Only
Speed in nanoseconds
L S 71V321 71V421
Low Power Standard Power 16K (2K x 8-Bit) MASTER 3.3V Dual-Port RAM w/ Interrupt 16K (2K x 8-Bit) SLAVE 3.3V Dual-Port RAM w/ Interrupt
3026 drw 17
NOTE: 1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.
Datasheet Document History
03/24/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 Added additional notes to pin configurations Changed drawing format Page 12 Changed open drain to totem-pole in Table III, note 1 Page 13 Deleted 'does not' in copy from Busy Logic Replaced IDT logo Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts Page 3 Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters-changed wording from "open" to "disabled" Changed 200mV to 0mV in notes Pages 4, 5, 7, 9 & 11 Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com
06/15/99: 10/15/99: 10/21/99: 11/12/99: 01/12/01:
08/22/01:
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
14 6.42

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